Suppression of vertical crosstalk in a plasma display panel

ABSTRACT

A method for controlling electrodes in a plasma display panel ( 815 ), includes applying a voltage Ve to a sustain electrode during a setting up of the sustain electrode ( 710 ) for an addressing operation, where Ve 2 &lt;Ve. Another method includes a) applying Ve 2  to the sustain electrode during the addressing, where the sustain electrode is associated with a scan electrode ( 714 ) in an electrode pair, and b) applying a voltage Vs 1  to the scan electrode during a discharging of the electrode pair after the addressing, where Ve 2 &lt;Vs 1.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to plasma display panels (PDPs), and moreparticularly, to an electronic waveform technique that minimizesvertical crosstalk in a PDP.

2. Background of the Art

Color PDPs are well known. FIG. 1 illustrates a prior art embodiment ofa color alternating current (AC) PDP, as disclosed in U.S. Pat. No.6,118,214 to Marcotte (hereinafter “the Marcotte '214 patent”), which isincorporated herein by reference. Transparent electrodes 11 are employedon a front panel. A front plate (not shown) includes horizontal pluralpairs of sustain electrodes 10 that connect transparent electrodes 11 toa sustain bus 12. A plurality of pairs of scan electrodes 14 arejuxtaposed to paired sustain electrodes 10, and both electrode sets arecovered by a dielectric layer (not shown) and a magnesium oxide (MgO)layer (not shown). A back plate (not shown) supports vertical barrierribs 16 and plural vertical column electrodes 18 (shown in phantom).Individual column electrodes 18 are covered with red, green, or blue(RGB) phosphors, as the case may be, to enable a full color display tobe achieved. The front and rear plates are sealed together and a spacetherebetween is filled with a dischargeable gas.

An electrode pair is defined as (a) a sustain electrode 10 (and itsadjacent transparent electrode 11) juxtaposed with (b) a scan electrode14 (and its adjacent transparent electrode 11). A pixel 20 is defined asan area that includes intersections of (i) an electrode pair of sustainelectrode 10 and scan electrode 14 on the front panel, and (ii) threecolumn electrodes 18 for red, green, and blue, respectively, on the backpanel. A subpixel corresponds to an intersection of a red, green or bluecolumn electrode with an electrode pair of a sustain electrode and ascan electrode. For example, subpixel 19 corresponds to an intersectionof a red column electrode 18 with an electrode pair of sustain electrode10 and scan electrode 14.

Operating voltage and power of the PDP are controlled by a discharge gap13 and a width of transparent electrode 11. The operating voltage of thePDP is controlled by the distance across the discharge gap 13, as thedistance controls the breakdown voltage for a given gas mixture.Furthermore, sufficient voltage must be applied so that the ensuing gasdischarge plasma is able to fully engulf the scan and sustain electrodepair. The power consumed by the discharge is affected by the surfacecapacitance of the electrode pair, which is proportional to electrodearea and inversely proportional to the dielectric thickness.

A width of sustain electrode 10 and a width of scan electrode 14 arechosen to produce a narrow discharge gap 13 and a wide inter-pixel gap15. When sufficient voltage is applied across discharge gap 13, the gaswill break down forming a discharge plasma. For a given applied voltage,the positively charged electrode is the anode and the negatively chargedelectrode is the cathode. The discharge plasma has two distinct regions,the positive column and the negative glow. The positive column consistspredominantly of fast moving electrons seeking the positive charge onthe surface of the anode electrode. Conversely, the negative glowcontains slow moving ions drifting toward and across the negativelycharged cathode electrode. The duration of the discharge is limited bythe amount of charge on the dielectric surfaces. Once the charge hasbeen transferred, the discharge self-extinguishes, with the cell voltageequaling zero, and the dielectric covering the electrodes is oppositelycharged. Within a sustain time period, this process is repeated byalternating the voltage polarity after each discharge completes.Inter-pixel gap 15 must be made sufficiently large to prevent theenergetic positive column of the plasma discharge from bridging theinter-pixel gap and corrupting an ON or OFF state of an adjacent pixel.The width of the transparent electrode 11 and the thickness of adielectric glass (not shown) over the electrode determine the pixel'sdischarge capacitance, which controls the discharge power and thereforebrightness. For a given discharge power/brightness, a number ofdischarges is chosen within sustain time periods to provide gray scaleswhich sum to meet the overall brightness requirement for the panel.

FIG. 2 shows a typical prior art block diagram of a PDP system 200. Ananalog video signal is input into logic 230 where the signal isdigitized, processed, and temporarily stored. Once a frame's worth ofdata is stored, logic 230 begins a process of displaying data through aseries of subfields, typically 8 to 12, as disclosed in U.S. Pat. No.5,724,054 to Shinoda.

FIG. 3 is a graph showing a division of a frame time into 8 subfields(i.e., SF1-SF8). During each addressing period lines Y1 through Y480 arescanned sequentially by row drivers 210, while video input is appliedthrough column drivers 225 to set each sub-pixel in the ON state asrequired by the video input. Each subsequent sustain period is weightedwith sustain pulses to achieve weighted light intensities for eachsubfield.

FIG. 4 shows a typical division of a subfield. Each subfield has a setupperiod, an addressing period, and a sustain period. The setup periodturns off any ON pixels, primes the MgO layer, and sets up all thepixels for addressing. Referring to both FIG. 2 and FIG. 4, during theaddressing period, a scan generator 205, in conjunction with row drivers210, sequentially drives each row low for addressing. Once a given rowis enabled, logic 230 loads column drivers 225 with image datacorresponding to individual RGB sub-pixels requiring illumination basedupon received image data. Column drivers 225 apply voltage Vx toselected column electrodes. The coincidence of a selected row and anapplied column voltage initiates a weak discharge that cascades into adischarge between the selected scan electrode and its neighboringsustain electrode. Once completed, the discharge has placed theaddressed sub-pixel in the ON state. Any column not driven will remainin the OFF state. While the addressing discharge does produce visiblelight, it is not of sufficient brightness to represent the imageproperly. Consequently, a sustain period follows the addressing periodafter the last row has been addressed. During the sustain period, scangenerator 205 and a sustain generator 220 supply alternating sustainpulses so that a momentary ac-plasma discharge occurs on an applicationof each pulse. Each sustain discharge produces ultra violet light thatexcites surrounding phosphor which in-turn produces visible light. Eachsubfield within a frame contains a sufficient number of sustain pulsesand in-turn discharges to achieve a desired brightness for eachsubfield. Since each sub-pixel can be addressed independently in eachsubfield, a large color palate is obtainable.

FIG. 5 a shows a prior art composite waveform between the scan andsustain electrodes. Due to a capacitive relationship of the scan andsustain electrodes, the composite waveform is simply an output of scangenerator 205 (FIG. 4 Scan waveform), minus an output of sustaingenerator 220 (FIG. 4 Sustain waveform). Note that applied data pulsesare not included in FIG. 5 a.

FIGS. 5 b-5 e show cell voltage waveforms for each pixel addressingsequence. A cell voltage is an AC coupled voltage present on a gas sideof a dielectric layer between a scan and sustain electrode pair. Thecell voltage is limited, positive and negative, by a breakdown voltageof the gas, Vbr and −Vr.

When the breakdown voltage is exceeded in either direction, two types ofdischarges can occur, a well-known negative resistance discharge and amore recently discovered positive resistance discharge. According toU.S. Pat. No. 5,745,086 to Weber, and referring to FIG. 4, if an appliedwaveform rises or falls slowly, as in rising and falling ramps of thesetup period t12 and t15, the gas will discharge having a positiveresistance characteristic, behaving much like a zener diode limiting thevoltage across the gas to the breakdown voltage Vbr. If the appliedvoltage exceeds the breakdown voltage sharply, as in the sustain periodst23, t24, a negative resistance or avalanche discharge occurs, whichreduces the cell voltage to zero. Once the cell voltage reaches zero,the discharge self extinguishes.

The addressing discharge is also a negative resistance discharge,exhibiting the characteristics of a positive column discharge asdisclosed in U.S. Pat. No. 6,184,848 to Weber (hereinafter “the Weber'848 patent”). The Weber '848 patent defines the positive columndischarge as having a trigger cell and a state cell. A panel topology issimilar to that of FIG. 1, but less transparent electrodes 11 therebycreating a large discharge gap. In the presence of a high cell voltage,due to an application of sustain pulses following an addressingoperation, a weak discharge forms between a positively charged backplate electrode and a negatively charged front electrode. Thisintersection is said to be a trigger cell. The weak discharge, inconjunction with the high cell voltage, yields a discharge where theplasma forms two clearly distinct regions, a negative glow and apositive column. The negative glow consists of slow moving positivelycharged ions, and the positive column consists of slow moving ions andrapidly moving electrons. The electrons move toward the positivelycharged anode, and the ions drift slowly toward the negatively chargedcathode. As the weak discharge strengthens, the negative glow expandsabout the trigger cell, and the positive column spreads along the backplate's phosphor layer to the positively charged state cell. Thedischarge completes when the wall charge is reversed between the triggercell and the state cell.

For the addressing discharge in the PDP of FIG. 1, the intersection ofthe column electrode and the selected scan electrode forms the triggercell, and the corresponding sustain electrode intersecting with the samecolumn electrode forms the state cell. At the completion of the setupperiod t16, each pixel is setup so that cell voltage is at the dischargelevel −Vr. When the pixel is addressed, a weal, discharge forms at theintersection of the selected scan electrode and at each of the drivenback plate column electrodes. The discharge develops producing apositive column which spreads along the positively charged back plateelectrode to the positively charged sustain electrode. As the electronsin the plasma move toward the anode, the anode looses its positivecharge and becomes negatively charged. Likewise, the negatively chargedcathode attracts positively charged ions and becomes positively charged.Hence, as the cell voltage is reduced to zero, the wall charge on thesustain electrode dielectric layer is reversed.

FIG. 5 b shows cell voltages for a previously OFF pixel, which is setupfor addressing, not addressed, and remains OFF in a latter sustainperiod. Specifically, a rising ramp t12 in a setup period rises,bringing the cell voltage above the breakdown voltage and clamps thecell voltage at Vbr. Voltage Ve being applied at t13, as shown in FIG.4, ensures that an address discharge will be strong enough for a firstsustain discharge to occur properly. A transition into the falling rampt13 and t14 reverses the cell voltage and the falling ramp t15 clampsthe cell voltage at −Vr. At the conclusion of the setup period, the cellvoltage is at −Vr. A row select pulse at time t17 in FIG. 4 exceeds thebreakdown voltage slightly due to a difference between Vrf and 0V. Sincethe falling ramp during time t15 stops at Vrf above 0V, a small negativevoltage is effectively applied when the row select pulse is applied attime t17 to exceed the breakdown voltage −Vr. Since this effectivenegative voltage, caused by Vrf is small and the width of the row selectpulse at t17 is narrow, no discharge activity occurs unless there is avideo input dictated data pulse on a data electrode coincident with therow select pulse at time t17 as shown in FIG. 4. In FIG. 5 b, no datapulse is applied, and so there is no discharge activity at time t17.Since an address discharge did not occur, the cell voltage produced bythe first sustain pulse at t21 is not greater the positive breakdownvoltage Vbr and no sustain discharge will occur.

FIG. 5 c shows the turn-on process for an OFF pixel. The setup periodoccurs as in FIG. 5 b and a data pulse (not shown) is applied to thecolumns at time t17 triggering an address discharge which returns thecell voltage to zero. Later at time t21, after the remaining rows havebeen addressed, the first sustain discharge will occur on any pixelwhich was addressed. For the first sustain pulse, the scan electrode isdriven high before lowering the sustain electrodes, unlike subsequentsustain pulses. This method of generating the first discharge prevents apremature discharge, which can form if the sustain electrode voltage ofVe, 220V is lowered before raising the scan electrode voltage to sustainvoltage Vs, 180V, due to the application of voltage Ve in the setupperiod as shown in FIG. 4 during addressing. Having been addressedpreviously, the breakdown voltage Vbr is exceeded, and a negativeresistance discharge will occur, again returning the cell voltage tozero. Each subsequent sustain pulse initiates another dischargeproducing the light of an ON pixel.

Following the first sustain discharge, the falling edge of the scanelectrodes lowers the cell voltage towards the negative breakdownvoltage −Vr. The subsequent rise of the other sustain electrodes addsmore voltage across the gas and exceeds the breakdown voltage −Vr,producing the next discharge. This process continues for the duration ofthe sustain period with the discharges alternating back and forth.

FIG. 5 d shows a re-addressing of an ON pixel. The application of thesetup pulse at time t11 causes the last negative resistance discharge ofthe previous subfield's sustain period. Since the cell voltage wasreturned to zero by the discharge, the rising ramp at t12 will notdischarge since the rising cell voltage does not exceed Vbr. The fallingramp limits the cell voltage to −Vr, as it did in FIGS. 5 b and 5 c. Attime t17, a data pulse is applied with the row select, a dischargeoccurs, and the pixel is returned to the ON state.

FIG. 5 e shows an ON pixel which is erased by the falling ramp t15 as inFIG. 5 d, however it is not re-addressed, and is OFF in the lattersustain period.

As disclosed in the Marcotte '214 patent, the paired front plateelectrode configuration of FIG. 1 has the advantage of reducedinter-electrode capacitance, which reduces the power dissipationresulting from charging and discharging of the inter-electrodecapacitance with each sustain pulse. However, there is an increasedprobability of vertical crosstalk. Vertical crosstalk occurs when adischarge at one discharge site spreads into a vertically adjacentdischarge site. The Marcotte '214 patent utilizes a large inter-pixelgap to help increase vertical pixel-to-pixel isolation. Note that theback plate barrier ribs provide horizontal pixel isolation but novertical isolation. The greatest probability of crosstalk occurs duringthe addressing discharge where the plasma discharge forms between aselected scan and data electrodes and the positive column spreads to thesustain electrode.

FIG. 6 shows the time sequenced discharge mechanics for an addressdischarge showing crosstalk discharge. The pictorial is a crosssectional view the PDP of FIG. 1 showing front plate electrodes on topand orthogonally oriented address electrode on the bottom, which iscovered by a phosphor layer. P1 refers to the red sub-pixel 19 of FIG. 1and a vertically adjacent red sub-pixel, P2 with inter-pixel gap 15separating P1 and P2. The time t0 for each row occurs with theapplication of the row select pulse at time t17 in conjunction with anapplied data pulse to the address electrode. The sub-pixels were setupby the falling ramp applied to the scan electrodes while Ve was appliedto the sustain electrodes. This places the negative charge on the scanelectrodes and the positive charge on the sustain and back plateelectrodes prior to t0. Vrf allows the row select pulse to slightlyexceed the breakdown voltage to help speed up the address discharge. Theapplication of voltage Vscan at time t16, in FIG. 4, by the row drivers210, acts as a row deselect voltage by reducing the negative voltage onthe non-selected rows so that the cell voltage on the scan electrodes isreduced. This prevents the addressing of one row from affecting theother rows in the display. The full cell voltage returns at time t17when the row is selected, and the breakdown voltage −Vbr is exceeded asshown in FIG. 5 b. The Vscan voltage is a de-select voltage and must behigh enough to ensure sufficient row to row isolation in the presence ofapplied column voltages.

If a data pulse is provided, at time t0 in FIG. 6 a weak discharge formsbetween the back plate address electrode and the active scan electrode,and at time t1, a negative resistance plasma discharge forms. At timet2, the availability of positive charge on the sustain electrodes allowsthe positive column to rapidly engulf the sustain electrode, and at timet3 can easily spread across the inter-pixel gap to the neighboringsustain electrode and thereby deplete the positive charge of theneighboring pixel P2. When P2's scan electrode is selected and thecolumn electrode is driven, the weak back to front discharge may form,however, without the positive charge on the sustain electrode, theplasma will not form, the scan electrode will maintain its negativecharge, and pixel P2 will remain off.

In a paper entitled “Symmetrically driven PDP, with minimized currentloops to reduce EMI” by Vossen et al. (hereinafter “the Vossen et al.paper”), there is disclosed the usage of interlaced addressing to reducecrosstalk in a PDP. With interlaced addressing, the odd rows areaddressed followed by the even rows. As such, any gas priming resultingfrom addressing the odd rows will be fully extinguished prior toaddressing the even rows. The Vossen et al. paper also talks of asymmetrically sustained PDP that uses the paired electrode configurationdescribed in the Marcotte '214 patent as helping to reduce verticalcrosstalk. However, the Vossen et al. paper does not describe or correctfor the form of vertical crosstalk described herein. Specifically, theVossen et al. paper describes addressing with the electrodes configuredas non-paired electrodes (i.e., scan, sustain, scan, sustain), whichdoes not have a common potential across an inter-pixel gap duringaddressing. In the non-paired case, a crosstalk discharge will in factgo in the wrong direction, discharging to an incorrect sustainelectrode. The use of interlaced addressing reduces this likelihood ofthis artifact.

SUMMARY OF THE INVENTION

There is provided a method for controlling electrodes in a plasmadisplay panel (PDP). One aspect of the method includes applying avoltage Ve to a sustain electrode during a setting up of the sustainelectrode for an addressing operation involving the sustain electrode,and applying a voltage Ve2 to the sustain electrode during theaddressing operation, where Ve2<Ve. This application of voltages weakensan address discharge of a sub-pixel.

Another aspect of the method includes (a) applying a voltage Ve2 to asustain electrode during an addressing operation involving the sustainelectrode, where the sustain electrode is associated with a scanelectrode in an electrode pair, and (b) applying a voltage Vs1 to thescan electrode during a discharging of the electrode pair after theaddressing operation, where Ve2<Vs1.

Yet another aspect of the method includes (a) applying a voltage Vs1 toa first scan electrode during a discharging of an electrode pair afteran addressing operation involving a sustain electrode, where the firstscan electrode is associated s with the sustain electrode in theelectrode pair, and (b) applying a voltage Vs2 to a second scanelectrode during the discharging, where the second scan electrode isadjacent to the first scan electrode, and where Vs2<Vs1.

There is also provided an apparatus for controlling electrodes in aplasma display panel. One aspect of the apparatus includes a circuitthat applies a voltage Ve to a sustain electrode during a setting up ofthe sustain electrode for an addressing operation involving the sustainelectrode, and a circuit that applies a voltage Ve2 to the sustainelectrode during the addressing operation, where Ve2<Ve.

Another aspect of the apparatus includes (a) a circuit that applies avoltage Ve2 to a sustain electrode during an addressing operationinvolving the sustain electrode, where the sustain electrode isassociated with a scan electrode in an electrode pair, and (b) a circuitthat applies a voltage Vs1 to the scan electrode during a discharging ofthe electrode pair after the addressing operation, where Ve2<Vs1.

Yet another aspect of the apparatus includes (a) a circuit that appliesa voltage Vs1 to a first scan electrode during a discharging of anelectrode pair after an addressing operation involving a sustainelectrode, where the first scan electrode is associated with the sustainelectrode in the electrode pair, and (b) a circuit that applies avoltage Vs2 to a second scan electrode during the discharging, where thesecond scan electrode is adjacent to the first scan electrode, and whereVs2<Vs1.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic representation of a conventional color PDP.

FIG. 2 is a block diagram of a conventional PDP system.

FIG. 3 is graph showing the division of frame time into 8 subfields.

FIG. 4 is a graph of conventional subfield waveforms.

FIG. 5 a is a graph of a conventional composite waveform between a scanelectrode and a sustain electrode, and FIGS. 5 b-5 e are graphs ofconventional cell voltage waveforms for pixel addressing sequences.

FIG. 6 is a schematic representation of discharge mechanics for anaddress discharge showing crosstalk discharge for the PDP of FIG. 1.

FIG. 7 is a schematic representation of a color PDP.

FIG. 8 is a block diagram of a PDP system providing vertical crosstalksuppression.

FIG. 9 is a graph of even and odd sustain electrode waveforms for a PDPemploying vertical crosstalk suppression.

FIG. 10 a is a graph of a composite waveform, and FIG. 10 b is a graphof a cell voltage waveform, for an even bank of electrodes.

FIG. 11 is a schematic representation of a cross-sectional view of theodd pixel discharge mechanics.

FIG. 12 is a schematic representation of a cross-sectional view of theeven pixel discharge mechanics.

FIG. 13 is a graph of waveforms in a system utilizing sequentialaddressing wherein sustain electrodes are enabled in conjunction withtheir corresponding scan electrodes.

FIG. 14 is a graph of even and odd sustain electrode waveforms for aPDP, where the sustain electrodes are separated into odd and evensustain buses.

FIG. 15 is a graph of even and odd sustain electrode waveforms for aPDP, where an increased voltage Vf is applied to the odd or even sustainelectrode buses.

FIG. 16 is a graph showing waveforms where a voltage applied to asustain electrode is reduced from a setup voltage Ve to a voltage Ve2at, or near, a sustain voltage Vs at a time of transition between asetup period and an addressing period, and where a voltage Vs1 isintroduced to strengthen the first sustain discharge.

FIG. 17 is a block diagram of a PDP system with circuitry that utilizesan isolation voltage to provide first sustain vertical crosstalksuppression, thus preventing a positive column of a first sustaindischarge from spreading across a scan electrode pair inter-pixel gap byreducing voltage on a neighboring scan electrode during the firstsustain discharge.

FIG. 18 is a graph of waveforms produced by the circuitry of FIG. 17.

FIGS. 19A and 19B are block diagrams of alternative switchingarrangements that may be employed by the boost circuits of the system inFIG. 17.

DESCRIPTION OF THE INVENTION

FIG. 7 is a schematic representation of a portion of a color PDPemploying address crosstalk suppression. The PDP is organized into rowsof pixels, three of which are shown, namely, a pixel 720 _(n) in row“n”, a pixel 720 _(n+1) in row “n+1”, and a pixel 720 _(n+2) in row“n+2”. The rows are regarded as “odd” and “even” in an alternatingpattern, where for example, row “n” is designated as an even row and row“n+1” is designated as an odd row.

The portion of the PDP shown in FIG. 7 includes an even sustain bus 712_(E) connected to a bank of even sustain electrodes 710 _(E), an oddsustain bus 712 _(O) connected to a bank of odd scan electrodes 710_(O), scan electrodes 714 _(n), 714 _(n+1) and 714 _(n+2), and columnelectrodes 718 _(R), 718 _(G) and 718 _(B) (for red, green, and blue,respectively). Each even sustain electrode 710 _(E) is adjacent to anodd sustain electrode 710 _(O). For example, even sustain electrode 710_(E) in row “n” is adjacent to odd sustain electrode 710 _(O) in row“n+1”. There is also a transparent electrode 711 associated with each ofsustain electrodes 710 _(E) and 710 _(O), and scan electrodes 714 _(n),714 _(n+1) and 714 _(n+2).

An intersection of a sustain electrode, a scan electrode and a columnelectrode, defines a subpixel. For example, a subpixel 719 _(R) isdefined for the intersection of sustain electrode 710 _(E), scanelectrode 714 _(n), and column electrode 718 _(R). Barrier ribs 716separate subpixels from one another. Each pixel is defined as a regionof intersection of a sustain electrode, a scan electrode, and threecolumn electrodes. For example, pixel 720 _(n) is defined at the regionof intersection of sustain electrode 710 _(E), scan electrode 714 _(n),and column electrodes 718 _(R), 718 _(G)and 718 _(B). An inter-pixel gap715 is defined for a region between adjacent pixels.

Each pixel includes a discharge gap where a sustain discharge forms. Forexample, in pixel 720 _(n), a discharge gap 713 is located between (a) atransparent electrode 711 associated with scan electrode 714 _(n) and(b) a transparent electrode 711 associated with even sustain electrode710 _(E).

An even/odd selector 820 drives odd sustain bus 712 _(O) via an oddsustain driver line 817 _(O), and drives even sustain bus 712 _(E) viaan even sustain driver line 817 _(E). Column driver 830 drives columnelectrodes 718 _(R), 718 _(G) and 718 _(B) via column driver lines 840_(R), 840 _(G) and 840 _(B), respectively. Row drivers 810 drive scanelectrodes 714 _(n), 714 _(n+1), and 714 _(n+2) via row driver lines 812_(n), 812 _(n+1), and 812 _(n+2). The operation of even/odd selector820, column driver 830 and row drivers 810 are further described inassociation with FIG. 8.

As mentioned earlier, FIG. 7 shows only a portion of the PDP. Inpractice, the PDP will include a plurality of rows and columns.Accordingly, column drivers 830 will drive many more columns than areshown in FIG. 7, and row drivers 810 will drive many more rows than areshown in FIG. 7.

FIG. 8 is a block diagram of a PDP system 800 employing verticalcrosstalk suppression during an addressing period. The principalcomponents of system 800 include a scan generator 805, row drivers 810,a PDP 815, even/odd selector 820, a sustain generator 825, columndrivers 830 and logic 835.

Sustain generator 825 operates in the same manner as sustain generator220 (FIG. 2), but supplies voltage Ve to even/odd selector 820 duringaddressing.

Even/odd selector 820 is a circuit that employs a method for controllingsustain electrodes in a PDP. The method includes (a) enabling a firstsustain electrode to produce an addressing discharge, and (b) disablinga second sustain electrode when the first sustain electrode is producingthe addressing discharge, where the first sustain electrode is adjacentto the second sustain electrode.

Even/odd selector 820 controls even sustain electrodes 710 _(E) and oddsustain electrodes 710 _(O). It supplies an isolation voltage (Viso) toeven sustain electrodes 710 _(E) via an output to sustain driver line817 _(E), and supplies Viso to odd sustain electrodes 710 _(O) via anoutput to sustain driver line 817 _(O). The purpose of Viso is furtherexplained below.

FIG. 9 is a graph of even and odd sustain electrode waveforms during anaddressing of an even row at time t17 (odd rows are isolated at t17).Assume that the waveforms are for scan electrode 714 _(n), even sustainelectrode 710 _(E) and odd sustain electrode 710 _(O). The X Datawaveform represents an output of column driver 830 to one of columndriver lines 840 _(R), 840 _(G) and 840 _(B). Typical operating voltagesfor the PDP of FIG. 7 operated with the waveforms of FIG. 9 would be asetup voltage Vsetup of 400V, a sustain voltage Vs of 180V, a Vscanvoltage of 120V, a ramp bias voltage Vrf of 10V, a setup/erase voltageVe of 220V, an isolation voltage Viso of 0 to 120V (Viso is typically atleast 60 volts below voltage Ve), and a data voltage Vx of 65V.

The voltage on even sustain electrode 710 _(E) is referenced to avoltage on scan electrode 714 _(n). The voltage on odd sustain electrode710 _(O) is referenced to a voltage on scan electrode 714 _(n+1). Thesereferences are established during the setup period. During the setupperiod, even/odd selector 820 provides Ve to, and thus enables, botheven sustain electrode 710 _(E) and odd sustain electrode 710 _(O).

At t25, the addressing period begins, and even/odd selector 820 reducesthe voltage supplied to even sustain electrode 710 _(E) to Viso thusreducing the difference of voltage, and therefore the magnitude, betweeneven sustain electrode 710 _(E) and scan electrode 714 _(n). Thisdisables the even bank for the first half of the addressing period. Notethat during the first half of the addressing period, odd sustainelectrode 710 _(O) is enabled. At time t26, even/odd selector 820restates the voltage on even sustain electrode 710 _(E) to Ve, andreduces the voltage on odd sustain electrode 710 _(O) to Viso, thusreducing the magnitude of the difference in voltage between odd sustainelectrode 710 _(O) and scan electrode 714 _(n+1). Thus, at time t26 theeven and odd banks switch roles for the second half of the addressingperiod so that the odd bank is disabled and the even bank is enabled. Attime t17, during the second half of the addressing period, even sustainelectrode 710 _(E) produces an addressing discharge to scan electrode714 _(n). Crosstalk between even sustain electrode 710 _(E) and oddsustain electrode 710 _(O) is suppressed by the lower potential (i.e.,Viso) on odd sustain electrode 710 _(O) at time t17. This is because theenabling voltage Ve on even sustain electrode 710 _(E) is referenced tothe voltage on scan electrode 714 _(n), and the disabling voltage Visoon odd sustain electrode 710 _(O), when referenced to the voltage onscan electrode 714 _(n) is a lower magnitude than the enabling voltageVe. Similarly, the row select and the respective column data aresynchronized by logic block 835 to sequence through the odd rows firstfollowed by the even rows.

In FIG. 9, a negative pulse on scan electrode 714 _(n) during theaddressing period indicates the time at which a particular pixel isaddressed. Such a pulse occurs at time t17. Note that also at time t17even sustain electrode 710 _(E) is at Ve (and therefore enabled) whileodd sustain electrode 710 _(O) is at Viso (and therefore disabled).Accordingly, the waveforms in FIG. 9 are for a case of addressing aneven row in PDP 815, and more particularly, row “n”.

In the first sustain cycle, at time t20 there is a rising edge for thevoltage on scan electrode 714 _(n), and at t21 there is a falling edgefor the voltage on even sustain electrode 710 _(E). The addressingdischarge that was produced by even sustain electrode 710 _(E) at timet17 allows even sustain electrode 710 _(E) to produce a first sustaindischarge during time t22.

FIG. 10 a is a graph of a composite waveform of the scan waveform andeven sustain waveform of FIG. 9, and FIG. 10 b is a graph of a cellvoltage waveform, for an OFF sub-pixel on the even bank of electrodes.Since the graph is that of an off sub-pixel, the breakdown voltage isonly exceeded during the two setup ramps where the cell voltage islimited to Vbr and −Vbr, approximately ±200V.

The composite waveform is formed by subtracting the sustain electrodevoltage from the scan electrode voltage. Assume for example, a case ofeven sustain electrode 710 _(E) and scan electrode 714 _(n). Reducingvoltage on even sustain electrode 71 _(E) from Ve to Viso at t25 for thefirst half of the addressing period causes an increase in the compositevoltage and thereby reduces the voltage across the gas. When the voltageon even sustain electrode 710 _(E) is increased from Viso to Ve duringthe second half of the addressing period, the cell voltage returns closeto the breakdown voltage −Vbr, so that the application of the row selectpulse at t17 slightly exceeds the breakdown voltage −Vbr.

FIGS. 11 and 12 show cross sectional views of pixel addressing dischargemechanics. More particularly, FIG. 11 shows the addressing dischargemechanics for an odd pixel P1, and FIG. 12 shows a neighboring evenpixel P2. In FIG. 11, P1's sustain electrode is tied to the enabled oddsustain bank, and is at a higher voltage, Ve, than the disabled evensustain electrode, at voltage Viso. The P1 address discharge isinitiated via an applied data pulse, however, the reduced positivevoltage on the even sustain electrode reduces the tendency of thepositive column to spread into the P2 pixel space. The lower the Visovoltage applied to the even electrode, the greater the isolationachieved.

The address discharge on P1 reverses the wall charge on the dielectricsurfaces of the pixel site; therefore, disabling the odd bank for thesecond half of addressing will result in an even greater isolationeffect from the P2 address discharge. Enabling the even sustainelectrodes returns them to their full positive voltage so that when P2is selected and a discharge forms, there is sufficient positive voltageon P2's sustain electrode available to form a strong address discharge.

FIG. 13 is a graph of scan and sustain electrode waveforms for a PDPwhere the voltage on the sustain electrodes is reduced to Viso toprovide cell-to-cell isolation. As each row is sequentially selected onthe scan side by a negative row select pulse at t17, a correspondingsustain electrode is returned to the sustain side addressing voltage Ve,thus providing a positive row select on the sustain side. Such anembodiment may be realized through the use of row drivers on the sustainside in place of even/odd selector 820 of FIG. 7.

FIG. 14 is a graph of even and odd sustain electrode waveforms for a PDPwhere the sustain electrodes are separated into odd and even sustainbuses. Row drivers 810 provide sequential negative going row selectpulses during the addressing period, while the sustain electrode voltagealternates between Viso and Ve as the row select pulse is applied toeach scan electrode. In FIG. 14, at time t17 there is a selection of anodd row, as the even sustain electrodes are driven to the isolationvoltage Viso, while the odd sustain electrodes are driven to the sustainside addressing voltage Ve.

FIG. 15 is a graph of even and odd sustain electrode waveforms for aPDP, where an increased forward voltage Vf of typically 10V higher thanvoltage Ve is applied to the odd or even sustain electrode buses. Thisarrangement provides additional voltage across the pixel to improve thepanel's addressing margin by increasing the charge transfer of theaddress discharge. Utilization of forward voltage Vf may also be appliedto the waveforms of FIGS. 13 and 14.

FIG. 16 is a graph showing waveforms where a voltage applied to asustain electrode is reduced from a setup voltage Ve to a voltage Ve2at, or near, a sustain voltage Vs, at a time of transition between asetup period and an addressing period. For example, Ve2=Vs±20%. Thewaveforms in FIG. 16 are for a scan voltage, an even sustain voltage, anodd sustain voltage and an X data voltage. These waveforms areindicative of voltages applied to an even sub-pixel and an oddsub-pixel. However, the scan voltage in FIG. 16 has a low-going rowselect pulse at time t17, which coincides with the even sustainelectrode being at voltage Vs and the odd sustain electrode beingdisabled by voltage Viso. Therefore the scan electrode shown in FIG. 16is paired with the even sustain electrode and shows an addressing of theeven sub-pixel. A pulse on the X data electrode at time t17 triggers anaddress discharge of the even sub-pixel. As explained below, thearrangement of waveforms in FIG. 16 performs an addressing operation ata voltage Ve2 that is less than setup voltage Ve to weaken the addressdischarge, and applies a boost voltage Vs1 to the scan electrode toproduce and strengthen an initial sustain discharge. The weaker addressdischarge is less likely to bridge the interpixel gap, where such abridge would otherwise cause crosstalk. The boost voltage applied to thescan electrode during the first sustain discharge compensates for theweak address discharge.

Just prior to time t25, during the setup period, the voltage on all oddand all even sustain electrodes is at a voltage Ve. On the scanelectrode, the application of a falling ramp at time t15 in conjunctionwith Ve being applied to the sustain electrodes produces a slow set updischarge at all sub-pixels in the display with a cell voltage equal tothe gas breakdown voltage, −Vbr. More, or less, charge can be placed oneach dielectric layer as voltage Ve is decreased or increased,respectively. Considering the even sustain electrode voltage representedin FIG. 16, at time t25, the even sustain electrode is deselected byapplying an isolation voltage Viso thereto. Although not shown in FIG.16, the odd sustain electrode is addressed at some time between time t25and time t26 when a row select pulse (similar to the pulse shown at timet17) is applied to the odd sustain electrode's corresponding scanelectrode, in conjunction with an X data pulse.

At time t26, the even sustain electrode is enabled for addressing withan application of a voltage Ve2, at or near Vs. By placing the evensustain electrode at a voltage Ve2 that is less than the setup voltageVe applied during the setup period prior to t25, less of a difference involtage exists between the even sustain electrode and its associatedscan electrode. That is, the cell voltage is reduced away from the gasbreakdown voltage. Also at time t26, the odd sustain electrode is drivento the isolation voltage Viso, thereby deselecting the odd sustainelectrode.

As previously described, the X data pulse initiates a discharge betweenthe X data electrode and the scan electrode bearing the row selectpulse. At time t17, there is an addressing operation involving the evensustain electrode, where the address discharge propagates from the scanelectrode to the even sustain electrode. The strength of the addressdischarge at t17 is proportional to the voltage between the scanelectrode and the even sustain electrode. The greater the differencebetween the voltage applied to the even sustain electrode during setup(Ve) and the voltage applied for addressing (Ve2), then at time t17, thelesser is the difference between the voltage (Ve2) on the even sustainelectrode and the voltage (0V) on the scan electrode, and the weaker thedischarge will be between the even sustain electrode and its scanelectrode. The weakened address discharge in conjunction with thepresence of the isolation voltage Viso on the neighboring odd sustainelectrode, prevents the address discharge from bridging the inter-pixelgap, even in a case of a very small interpixel gap, e.g., less than 200microns.

A boost voltage Vs1, which is greater than the standard sustain voltageVs, is applied to the scan electrode at time t20. At time t21, thesustain electrodes are returned to 0V, initiating the first sustaindischarge. During time interval t22, in the first sustain cycle, aninitial sustain discharge occurs at all sub-pixels that were addressedduring the addressing period. For example, in FIG. 16, an initialsustain discharge occurs at time t21 as the voltage on the even sustainelectrode transitions from Ve2 to 0V. The larger voltage, i.e., Vs1,applied to the scan electrode during the first sustain discharge in thefirst sustain cycle compensates for a reduced wall charge transfer thatoccurred during the address discharge at time t17 because the voltage onthe even sustain electrode was reduced from Ve to Ve2. For the remainderof the sustain period, after the first sustain cycle, the scanelectrodes are driven to Vs rather than Vs1 during discharging of theircorresponding sustain electrodes.

Following the initial sustain discharge during time interval t22, thesustaining voltage Vs is applied to the sustain electrodes prior to theremoval of the Vs1 voltage from the scan electrodes. Time intervals t23and 24 are transition intervals. For example, in FIG. 16, after theinitial sustain discharge during time interval t22, during time intervalt23 the voltage on the even sustain electrode transitions from 0V to Vs.More particularly, during time interval t23 the voltages on the even andodd sustain electrodes transition from 0V to Vs, and the voltage on thescan electrode transitions from Vs1 to 0V, initiating a second sustaindischarge. During time interval t24, the voltages on the even and oddsustain electrodes transition from Vs to 0V, and the voltage on the scanelectrode transitions from 0V to Vs. The second sustain discharge occursafter the end of time interval t23 and before the beginning of timeinterval t24. Overlapping the sustain pulse edges during time intervalt23, that is by concurrently driving both the even and odd sustainelectrodes from 0V to Vs, prevents a premature discharge from occurringwith the removal of Vs1 prior to applying Vs to the sustain electrodes.With the overlap, the second discharge occurs with the fall of the scanelectrode voltage at the end of time interval t23. However, with thelower sustain voltage Vs applied to the sustain electrodes during timeinterval t23, the transitions during time interval t24 need not beoverlapped.

While the usage of the boost voltage Vs1 is to compensate for thevoltage reduction of the sustain electrodes from voltage Ve appliedduring setup to voltage Ve2 during addressing, such a usage of boostvoltage Vs1 may also be applied in a PDP apparatus that does not employthe voltage reduction of Ve to Ve2 in an effort to increase the strengthof the first sustain discharge.

Like the address discharge, due to the time delay from addressingcausing a lack of discharge priming, and like the inherent weakness andvariability in the address discharges themselves, the first sustaindischarge is also slow to develop. As the first sustain discharge formsa positive column spreads across the sub-pixel site's scan electrode. Ifthe site across the scan electrode inter-pixel gap was addressed, andwhose first sustain discharge is slightly delayed, the positive columnof the first discharging site can spread across the inter-pixel gap andprevent the neighboring site from discharging. Thus, the first sustaindischarge may exhibit a similar vertical crosstalk failure mechanism asin addressing where the positive column spreads across the inter-pixelgap separating adjacent scan electrodes. Accordingly, a first sustaindischarge crosstalk suppression technique may be employed similarly tothe vertical crosstalk suppression technique employed during theaddressing period.

FIG. 17 is a block diagram of a PDP system 1800, incorporating firstsustain crosstalk suppression that separates the first sustain dischargeinto two separate discharges, i.e., a discharge of the odd rows and adischarge of the even rows.

FIG. 18 is a graph of waveforms produced by the circuitry of FIG. 17.More specifically, FIG. 18 shows waveforms for an even scan electrode,an odd scan electrode, an even sustain electrode, an odd sustainelectrode and an X data electrode. FIG. 18 shows a boost technique,similar to that of FIG. 16, applied separately to the odd scanelectrodes followed by the even scan electrodes between times t20 andt29.

As in system 800, which employs the technique of vertical crosstalksuppression during the addressing period, system 1800 utilizes a voltageisolation to prevent a positive column of a first sustain discharge fromspreading across a scan electrode pair inter-pixel gap by reducingvoltage on a neighboring scan electrode. A higher voltage is applied toone scan electrode in the pair while a lower isolation voltage isapplied to a neighboring electrode. After the discharge occurs, thevoltages can alternate to discharge the other scan electrode therebydividing the first sustain discharge into two discharges. For example, adischarge of the even rows followed by a discharge of the odd rows, or adischarge of the odd rows followed by a discharge of the even rows.

System 1800 includes a PDP 815, and circuitry for even/odd selector 820,column drivers 830, and sustain generator 825, as previously describedfor system 800. System 1800 further includes circuitry for a scangenerator 1805, an odd boost driver 1801, an even boost driver 1802, oddrow drivers 1803, even row drivers 1804, multiplexers 1806 and 1807, anda logic circuit 1835.

Sustain side circuitry is configured with sustain generator 825,even/odd selector 820, and multiplexer 1807. Sustain generator 825includes a voltage Ve2 to drive the sustain electrodes during theaddressing period shown in FIG. 18, while Ve drives the sustainelectrodes during the falling ramp of the setup period during time t15.Ve2 can be less than, equal to, or greater than Vs depending on theoperating characteristics of PDP 815, while Ve is typically greater thanor equal to Vs. Even/odd selector 820, separates the output from sustaingenerator 825 into even and odd sustain buses so that isolation voltageViso may be applied independently to either the even or odd sustainbuses. Multiplexer 1807 denotes the interdigitation of the odd and evenbuses into sustain connections to PDP 815.

Logic circuit 1835 controls the operation of system 1800. Logic circuit1835 is responsible for waveform timing control and video datasynchronization between the video input and the display.

Scan generator 1805 generates a base waveform that is used for drivingboth of the even scan electrodes and the odd scan electrodes. Scangenerator 1805 outputs sustain pulses during the sustain period up to avoltage Vs. During the setup period, a rising ramp during time t12 isdriven to voltage Vsetup and a falling ramp during time t15 is driven tovoltage Vrf.

Odd and even boost drivers 1801 and 1802 receive the waveform from scangenerator 1805 and route it to odd row drivers 1803 and even row drivers1804, respectively. Note that odd and even boost drivers 1801 and 1802also receive a voltage, i.e., boost voltage Vboost, the purpose of whichis further described below. Logic circuit 1835 controls odd and evenboost drivers 1801 and 1802. Referring to odd boost driver 1801, logiccircuit 1835 controls it to either (a) route the waveform from scangenerator 1805 to odd row drivers 1803, or (b) produce a boost voltageVs1 (see FIG. 18) that is passed to odd row driver 1803. Likewise, logiccircuit 1835 controls even boost driver 1802 to either (a) route thebase waveform to even row drivers 1804, or (b) produce boost voltage Vs1for even row drivers 1804.

During the first sustain cycle, scan generator 1805 outputs voltage Vs2.Boost drivers 1801 and 1802 selectively output voltage Vs2 or the boostvoltage Vs1 during the first sustain cycle. At all other times boostdrivers 1801 and 1802 pass through the waveform produced by scangenerator 1805.

Odd row drivers 1803 drive odd rows of scan electrodes, and even rowdrivers 1804 drive even rows of scan electrodes. Thus, the row driversare partitioned into even and odd banks. Row drivers 1803 and 1804 driveindividual display rows and can switch each of their respective outputsbetween (a) the output of their respective boost driver 1801, 1802through a lower output drive transistor (not shown), or (b) a floatingversion of voltage Vscan, typically 120V, through an upper output drivetransistor (not shown). Odd row drivers 1803 float on odd boost driver1801, and even row drivers 1804 float on even boost driver 1802.

Referring to FIG. 18, between times t25 and t26 the odd rows areaddressed sequentially by the odd row drivers, with a given odd rowselected at time t27. During this time interval, the even sustainelectrodes are suppressed by the isolation voltage Viso, and the evenscan electrodes are de-selected by voltage Vscan.

During the addressing period, scan generator 1805 outputs 0V. Alsoduring the addressing period, row drivers 1803 and 1804 output (a) thevoltage Vscan to all unselected rows, and (b) at time t17, the voltage0V, from scan generator 1805, to a selected row. At time t17, on theeven scan electrode there is shown a row select pulse, which isgenerated by the even row drivers 1804. Thus, that particular even scanelectrode is regarded as being selected at time t17. Even rows areselected sequentially between times t26 and t19. When an even row is notbeing selected, its corresponding even scan electrode voltage is drivento Vscan. Also at time t17, there is an addressing operation involvingthe even sustain electrodes where the even sustain electrodes are drivento a voltage Ve2 near Vs while the odd sustain electrodes are deselectedby being driven to the isolation voltage, Viso. If the data electrodesare driven with the X data voltage Vx, an address discharge will occurat each intersecting data electrode and selected row electrode.

The address discharge is initiated by a small discharge between theXdata electrode and the selected scan electrode. Once initiated, thedischarge forms a positive column that spreads over to the associatedsustain electrode, and current flows from the sustain electrode to thescan electrode. The magnitude of the current and therefore the strengthof the discharge is related to the amount of positive voltage, Ve, onthe sustain electrode. Consequently, reducing the voltage on the sustainelectrodes from Ve to Ve2 for addressing reduces the discharge currentand therefore reduces the strength of the discharge. Since the positivecolumn is capable of bridging the interpixel gap, reducing the dischargestrength will reduce the likelihood of the positive column from spanningthe interpixel gap and so vertical crosstalk during addressing isreduced. The voltage Ve2 is responsible for the wall charge transfer ofthe address discharge, and thus provides the ON state wall voltage forthe sustain period.

After addressing the desired pixels in each row, the sustain periodbegins. Each sustain cycle consists of two discharges, first withcurrent flow from scan to sustain side due to a sustain pulse applied tothe scan side, second with current flowing from sustain to scan side dueto a sustain pulse applied to the sustain side. The first sustaindischarge of the first sustain cycle is separated into a discharge ofthe odd row sub-pixels, followed by a discharge of the even rowsub-pixels. While addressing was performed at time t17, with the sustainelectrodes at a high voltage and the scan electrodes at a low voltage,the first sustain discharge has the opposite polarity of the addressdischarge with the sustain electrodes low and the scan electrodes high.

For the time between t20 and t29, scan generator 1805 outputs a voltageVs2. In an exemplary embodiment of system 1800, sustain voltage Vs is185V and voltage Vs2 is approximately 135V, i.e., 50V less that sustainvoltage Vs. At time t20, odd boost driver 1801 produces boost voltageVs1. Odd row drivers 1803 pass boost voltage Vs1 through theaforementioned lower output drive transistors to multiplexer 1806, whichdirects boost voltage Vs1 to the odd rows of PDP 815. Logic circuit 1835controls even boost driver 1802 to pass through voltage Vs2 from scangenerator 1805 to even row drivers 1804, which pass level Vs2 out to theeven rows of the PDP 815 through multiplexer 1806.

At time t22, the even and odd sustain electrodes are low, the odd scanelectrodes are at boost voltage Vs1, and the odd rows will produce theirfirst sustain discharge between the odd scan electrode and itsassociated odd sustain electrode. The positive column of the dischargewill envelop the odd scan electrode, however it will be less likely tobridge the interpixel gap to a neighboring even scan electrode, sincethe even scan electrodes are driven with the lower voltage Vs2. For ONsub-pixels, the total cell voltage, is the wall voltage resulting fromaddressing, Ve2, plus the applied first sustain voltage Vs1. Thus as Ve2is reduced, Vs1 is increased to provide sufficient voltage to dischargethe previously addressed sub-pixels.

At time t28, both boost drivers 1801 and 1802 switch their operatingmodes so that odd boost driver 1801 passes voltage Vs2 from scangenerator 1805, and even boost driver 1802 outputs boost voltage Vs1. Attime t29, scan generator 1805 produces voltage 0V, and even boost driver1802 selects scan generator 1805, thus returning all scan electrodes to0V. Voltage Vs2 is high enough to prevent a premature second sustaindischarge from forming on the odd rows between times t28 and t29 beforetime t23.

In the first sustain cycle, (1) the odd rows are discharged during timet21, then (2) the even rows are discharged during time t22, and then (3)the odd rows and even rows are simultaneously discharged between timest23 and t24. After the first sustain cycle, for the remainder of thesustain period, both odd rows and even rows are dischargedsimultaneously. The technique of not applying boost voltage Vs1 to rowsadjacent to a discharging site suppresses the positive column frombridging the inter-pixel gap and is conceptually similar to theapplication of the isolation voltage Viso to the sustain electrodes, asdescribed earlier. By separating and controlling the first sustaindischarge, that is, by first discharging the odd rows and thendischarging the even rows, or vice versa, vertically adjacent sub-pixelsites are fully discharged and primed so that cross-talk in the secondand subsequent sustain discharges is prevented for typical operatinglevels of sustain voltage Vs, which is less than the boost voltage Vs1.Therefore, vertical crosstalk is less likely to occur during the secondand subsequent sustain discharges.

As previously stated, row drivers 1803 and 1804 are controlled by logiccircuit 1835 to activate the lower output drive transistors of rowdrivers 1803 and 1804 during the first sustain cycle, and subsequentsustain cycles. If logic circuit 1835 activates the upper output drivetransistors of odd row drivers 1803 applying voltage Vscan, betweentimes t20 and t28 to discharge the odd rows, and then having even rowdrivers 1804 apply voltage Vscan between the times t28 and t29, then thesame waveform of FIG. 18 can be obtained without the need for the oddand even boost drivers 1801 and 1802. Thus, if voltage Vs1 minus Vs2 isequal to Vscan, then boost drivers 1801 and 1802 may be eliminated.

FIGS. 19A and 19B are block diagrams of alternative switchingarrangements that may be employed by boost circuits 1801 and 1802 toproduce boost voltage Vs1. In the arrangement of FIG. 19A, boost voltageVs1 is produced by selecting a summation of Vs2 and Vboost, where Vboostis a positive voltage. Thus, Vs1=Vs2+Vboost. In the arrangement of FIG.19B, Vs1 is produced by selecting Vboost, where Vboost>Vs2. Thus,Vs1=Vboost. Resultantly, for the arrangements in both of FIGS. 19A and19B, Vs1>Vs2.

It should be understood that the foregoing description is onlyillustrative of the invention. Various alternatives and modificationscan be devised by those skilled in the art without departing from theinvention. For instance, this invention is applicable other AC PDP andwaveform configurations, where an address discharge extends across apixel and can spread across an inter-pixel gap, seeking positive chargeon an adjacent sustain electrode. The present invention is intended toembrace all such alternatives, modifications and variances that fallwithin the scope of the appended claims.

1. A method for controlling electrodes in a plasma display panel,comprising: applying a voltage Ve to a sustain electrode during asetting up of said sustain electrode for an addressing operationinvolving said sustain electrode; applying a voltage Ve2 to said sustainelectrode during said addressing operation, wherein Ve2<Ve, and whereinsaid sustain electrode is associated with a scan electrode in anelectrode pair; applying a voltage Vs1 to said scan electrode during afirst discharging of said electrode pair after said addressingoperation; applying a voltage Vs to said sustain electrode during asecond discharging of said electrode pair after said addressingoperation, wherein Vs<Vs1; and applying said voltage Vs to said scanelectrode during a third discharging of said electrode pair after saidaddressing operation.
 2. The method of claim 1, wherein Ve2<Vs1.
 3. Themethod of claim 1, wherein Ve2=Vs±20%.
 4. The method of claim 1, whereinsaid sustain electrode is a first sustain electrode and adjacent to asecond sustain electrode, and wherein said method further comprises:applying a voltage Viso to said second sustain electrode when applyingsaid voltage Ve2 to said first sustain electrode during said addressingoperation, wherein Viso<Ve2.
 5. The method of claim 1, wherein saidmethod further comprises applying a negative sloping voltage to saidscan electrode during said application of said voltage Ve to saidsustain electrode.
 6. The method of claim 1, wherein said scan electrodeis a first scan electrode, wherein said first scan electrode is adjacentto a second scan electrode, and wherein said method further comprises:applying a voltage Vs2 to said second scan electrode during adischarging of said electrode pair after said addressing operation,wherein Vs2<Vs1.
 7. The method of claim 6, wherein Vs2<Ve2<Vs1.
 8. Themethod of claim 6, wherein said electrode pair is a first electrodepair, wherein said second scan electrode is a part of a second electrodepair, and wherein said method further comprises: applying said voltageVs1 to said second scan electrode and said voltage Vs2 to said firstscan electrode during a discharging of said second electrode pair.
 9. Amethod for controlling electrodes in a plasma display panel, comprising:applying a voltage Ve2 to a sustain electrode during an addressingoperation involving said sustain electrode, wherein said sustainelectrode is associated with a scan electrode in an electrode pair;applying a voltage Vs1 to said scan electrode during a first dischargingof said electrode pair after said addressing operation, wherein Ve2<Vs1;applying a voltage Vs to said sustain electrode during a seconddischarging of said electrode pair after said addressing operation,wherein Vs<Vs1; and applying said voltage Vs to said scan electrodeduring a third discharging of said electrode pair after said addressingoperation.
 10. The method of claim 9, further comprising: applying avoltage Ve to said sustain electrode during a setting up of said sustainelectrode for said addressing operation, wherein Ve2<Ve.
 11. The methodof claim 9, further comprising: applying a voltage Vs to said sustainelectrode during a discharging of said electrode pair, whereinVe2=Vs±20%.
 12. The method of claim 9, wherein said sustain electrode isa first sustain electrode and adjacent to a second sustain electrode,and wherein said method further comprises: applying a voltage Viso tosaid second sustain electrode when applying said voltage Ve2 to saidfirst sustain electrode during said addressing operation, whereinViso<Ve2.
 13. The method of claim 9, further comprising: applying avoltage Ve to said sustain electrode during a setting up of said sustainelectrode for said addressing operation; and applying a negative slopingvoltage to said scan electrode during said application of said voltageVe to said sustain electrode, wherein Ve2<Ve.
 14. The method of claim 9,wherein said scan electrode is a first scan electrode and adjacent to asecond scan electrode, and wherein said method further comprises:applying a voltage Vs2 to said second scan electrode during adischarging of said electrode pair, wherein Vs2<Vs1.
 15. The method ofclaim 14, wherein Vs2<Ve2<Vs1.
 16. The method of claim 14, wherein saidelectrode pair is a first electrode pair, wherein said second scanelectrode is a part of a second electrode pair, and wherein said methodfurther comprises: applying said voltage Vs1 to said second scanelectrode and said voltage Vs2 to said first scan electrode during adischarging of said second scan electrode pair.
 17. A method forcontrolling electrodes in a plasma display panel, comprising: applying avoltage Vs1 to a first scan electrode during a discharging of anelectrode pair after an addressing operation involving a sustainelectrode, wherein said first scan electrode is associated with saidsustain electrode in said electrode pair; and applying a voltage Vs2 toa second scan electrode during said discharging, wherein said secondscan electrode is adjacent to said first scan electrode, with nointervening sustain electrode between said first and second scanelectrodes, and wherein Vs2<Vs1.
 18. The method of claim 17, furthercomprising: applying a voltage Ve to said sustain electrode during asetting up for said addressing operation; and applying a voltage Ve2 tosaid sustain electrode during said addressing operation, wherein Ve2<Ve.19. The method of claim 17, further comprising: applying a voltage Ve2to said sustain electrode during said addressing operation, whereinVs2<Ve2<Vs1.
 20. The method of claim 17, wherein said discharging is afirst discharging of said electrode pair after said addressingoperation, and wherein said method further comprises: applying a voltageVs to said sustain electrode during a second discharging of saidelectrode pair after said addressing operation, and applying saidvoltage Vs to said scan electrode during a third discharging of saidelectrode pair after said addressing operation, wherein Vs<Vs1.
 21. Themethod of claim 17, further comprising: applying a voltage Ve2 to saidsustain electrode during said addressing operation; and applying avoltage Vs to said sustain electrode during said discharging, whereinVe2=Vs±20%.
 22. The method of claim 17, further comprising: wherein saidsustain electrode is a first sustain electrode and adjacent to a secondsustain electrode, and wherein said method further comprises: applying avoltage Ve2 to said first sustain electrode during said addressingoperation; and applying a voltage Viso to said second sustain electrodewhen applying said voltage Ve2 to said first sustain electrode duringsaid addressing operation, wherein Viso<Ve2.
 23. The method of claim 17,further comprising: applying a negative sloping voltage to said firstscan electrode during a setting up of said sustain electrode for saidaddressing operation.
 24. The method of claim 17, wherein said electrodepair is a first electrode pair, wherein said second scan electrode is apart of a second electrode pair, and wherein said method furthercomprises: applying said voltage Vs1 to said second scan electrode andsaid voltage Vs2 to said first scan electrode during a discharging ofsaid second electrode pair, after said discharging of said firstelectrode pair.
 25. An apparatus for controlling electrodes in a plasmadisplay panel, comprising: a circuit that applies a voltage Ve to asustain electrode during a setting up of said sustain electrode for anaddressing operation involving said sustain electrode; a circuit thatapplies a voltage Ve2 to said sustain electrode during said addressingoperation, wherein Ve2<Ve, and wherein said sustain electrode isassociated with a scan electrode in an electrode pair; a circuit thatapplies a voltage Vs1 to said scan electrode during a first dischargingof said electrode pair after said addressing operation; a circuit thatapplies a voltage Vs to said sustain electrode during a seconddischarging of said electrode pair after said addressing operation,wherein Vs<Vs1; and a circuit that applies said voltage Vs to said scanelectrode during a third discharging of said electrode pair after saidaddressing operation.
 26. An apparatus for controlling electrodes in aplasma display panel, comprising: a circuit that applies a voltage Ve2to a sustain electrode during an addressing operation involving saidsustain electrode, wherein said sustain electrode is associated with ascan electrode in an electrode pair; a circuit that applies a voltageVs1 to said scan electrode during a first discharging of said electrodepair after said addressing operation, wherein Ve2<Vs1; a circuit thatapplies a voltage Vs to said sustain electrode during a seconddischarging of said electrode pair after said addressing operation,wherein Vs<Vs1; and a circuit that applies said voltage Vs to said scanelectrode during a third discharging of said electrode pair after saidaddressing operation.
 27. An apparatus for controlling electrodes in aplasma display panel, comprising: a circuit that applies a voltage Vs1to a first scan electrode during a discharging of an electrode pairafter an addressing operation involving a sustain electrode, whereinsaid first scan electrode is associated with said sustain electrode insaid electrode pair; and a circuit that applies a voltage Vs2 to asecond scan electrode during said discharging, wherein said second scanelectrode is adjacent to said first scan electrode, with no interveningsustain electrode between said first and second scan electrodes, andwherein Vs2<Vs1.